1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. In particular, the present invention relates to an electrically erasable and programmable read only memory (hereinafter, referred to as an xe2x80x9cEEPROMxe2x80x9d). More specifically, the present invention relates a nonvolatile semiconductor memory using a multi-valued technique. The present invention is effective for a nonvolatile semiconductor memory with a channel length of 0.01 to 1 xcexcm (preferably, 0.01 to 0.5 xcexcm). Furthermore, the present invention relates to a semiconductor device having a nonvolatile semiconductor memory.
In this specification, the EEPROM refers to all the electrically erasable and programmable read only memories, and includes, for example, a full-function EEPROM and a flash memory. Furthermore, unless otherwise specified, the terms xe2x80x9cnonvolatile memoryxe2x80x9d and xe2x80x9cnonvolatile semiconductor memoryxe2x80x9d and the term xe2x80x9cEEPROMxe2x80x9d are used interchangeably. Furthermore, a semiconductor device refers to all the devices that function by utilizing semiconductor characteristics, and include, for example, electro-optical devices such as a microprocessor, a liquid crystal display device and an EL display device, and electronic apparatus provided with a microprocessor or an electro-optical device.
2. Description of the Related Art
The EEPROM is known as a memory such as a nonvolatile semiconductor memory. Since the EEPROM is a nonvolatile memory, unlike other semiconductor memories, i.e., a dynamic random access memory (DRAM) and a static RAM (SRAM), data are not lost even when a power source is turned off. Furthermore, compared with another nonvolatile memory, i.e., a magnetic disk, the EEPROM has excellent features in terms of an integration density, shock resistance, power consumption, a write/read speed, and the like. Because of these features, there is a tendency that the EEPROM is used as an alternative to various memories such as a magnetic disk and a DRAM.
In particular, the integration density of the EEPROM is being remarkably enhanced. More specifically, the integration density thereof is being increased at a very high pace (i.e., about twice per year). It is expected that the mass-production of the EEPROM with a gigabit capacity will be realized in the near future. Accordingly, the EEPROM will overtake the DRAM in terms of an integration density. Examples of a technique for such enhancement of an integration density include improvement of a circuit configuration, a fine processing technique, and a multi-valued technique.
Regarding the circuit configuration, a full-function EEPROM with a structure of 2 transistors/cell has been improved to a flash memory with a structure of 1 transistor/cell. Furthermore, a NOR-type flash memory requiring a cell area of 10 F2 (F is a minimum processing size) has been improved to a NAND-type flash memory realizing a cell area of 5 F2.
The fine processing technique is the most important technique for promoting a high integration density, miniaturization, and a low cost in substantially all the semiconductors such as an IC, an LSI, a VLSI, and a ULSI. In the EEPROM, a fine processing technique is always introduced in the same way as in the other ICs and the like, and is being developed in accordance with the scaling law.
Furthermore, as a method for enhancing the integration density of a memory, a multi-valued technique is recently being paid attention to. The multi-valued technique refers to a technique for retaining data with three or more values per memory cell. Conventionally, a method for controlling a charge accumulation amount of a floating gate to distinguish three or more states from each other has been developed. A flash memory with four values have already been produced.
As described above, in the EEPROM, remarkable enhancement of an integration density has been achieved by the circuit configuration, the fine processing technique, and the multi-valued technique. In order to further enhance an integration density, it is considered that the fine processing technique and the multi-valued technique are becoming more and more important. However, there are a number of problems in the fine processing technique and the multi-valued technique.
Regarding the fine processing, a scaling limit of the EEPROM is considered to be 0.12 to 0.15 xcexcm. There are some factors that determine the scaling limit. Examples thereof include a fine processing limit, a short channel effect, and reliability of a tunnel oxide film. Particularly, in an EEPROM requiring an operating voltage higher than that of an ordinary transistor, the short channel effect is a serious problem, and even though fine processing is possible, the EEPROM may not function as a memory due to the short channel effect.
The short channel effect collectively refers to various phenomena that occur in the case where the channel length of a transistor is shortened. Examples of the phenomena include a punchthrough phenomenon, degradation of subthreshold characteristics (increase in an S value), and a decrease in a threshold voltage. The short channel effect is mostly caused by a depletion layer region spreading from a drain region. Thus, it is a problem how to suppress the spread of a depletion layer region.
Furthermore, regarding the multi-valued technique, in the case of using a conventional method for controlling a charge accumulation amount of a floating gate electrode, it is considered to be difficult to realize the control of variation in a charge accumulation amount, satisfactory charge retention characteristics, and satisfactory read characteristics. Although a flash memory with four values has been realized by the conventional method, in order to further enhance the multi-valued technique, the development of a multi-valued technique different from the conventional method is considered to be required.
The present invention has been made in view of the above, and it is an object of the present invention to effectively suppress a short channel effect that occurs due to fine processing, and to allow a cell to have multi values by a method completely different from a multi-valued technique according to a conventional method for controlling a charge accumulation amount of a floating gate electrode. It is another object of the present invention to provide a nonvolatile memory with a very high integration density.
According to the present invention, in order to suppress a short channel effect caused by fine processing, a plurality of local impurity regions are formed in an active region of a memory transistor. More specifically, impurity regions are formed in a stripe shape in a channel length direction. Impurities having conductivity reverse to that of the impurities used for source and drain regions are used for the impurity regions provided in a stripe shape.
In this specification, a region surrounded by a source region, a drain region, and an element isolation region is referred to as an xe2x80x9cactive regionxe2x80x9d, and the active region is further separated into impurity regions provided in a stripe shape and channel forming regions.
The present invention is intended to be applied to a fine nonvolatile memory. More specifically, the present invention is effective for a nonvolatile semiconductor memory having a channel length of 0.01 to 1 xcexcm (preferably, 0.01 to 0.5 xcexcm), a width of an impurity region of 0.01 to 1 xcexcm (preferably, 0.01 to 0.5 xcexcm), and a width of a channel forming region of 0.01 to 1 xcexcm (preferably, 0.01 to 0.5 xcexcm).
In a fine transistor, a procedure for providing local impurity regions in an active region is disclosed in Japanese Patent Application Laid-open No. Hei 10-65162. In this publication, it is described that by providing local impurity regions in an active region, the spread of a depletion layer from a drain region can be suppressed, and a short channel effect can be suppressed while a high ON current is maintained.
In the above-mentioned publication, since the effect of suppressing a depletion layer is taken as if the depletion layer was pinned, the term xe2x80x9cpinningxe2x80x9d is defined as xe2x80x9csuppressionxe2x80x9d. Furthermore, an impurity region for pinning a depletion layer is referred to as a xe2x80x9cpinning regionxe2x80x9d.
According to the present invention, as a more important point, a multi-valued memory transistor is realized by utilizing a memory transistor using a pinning region. According to the present invention, considering that a transistor configuration using pinning regions has a plurality of channel forming regions, a memory transistor with multi values is realized by assigning one value or one bit of data to each channel forming region.
In this specification, in the case of distinguishing a memory transistor having pinning regions from a conventional memory transistor, the memory transistor using pinning regions is particularly referred to as a xe2x80x9cpinning memory transistorxe2x80x9d. The pinning memory transistor may be merely referred to as a memory transistor if it is apparent.
The pinning memory transistor of the present invention is characterized in that a floating gate electrode is provided on each of a plurality of channel forming regions via a first gate insulating film, and an electric potential is applied independently to a plurality of pinning regions. Because of this configuration, one value or one bit of data can be stored in each floating gate electrode (each channel forming region).
Hereinafter, a method for operating the pinning memory transistor will be briefly described. Write and erasure of multi-valued data is conducted by using a tunneling current between a floating gate electrode and a pinning region. In the case where a memory transistor is of an n-channel type, electrons are injected to a selected floating gate electrode and discharged from all of the floating gate electrodes. Furthermore, in the case where a memory transistor is of a p-channel type, electrons are discharged from a selected floating gate electrode and injected to all of the floating gate electrodes.
A read method can be classified into the case where one value of data is assigned to each floating gate electrode (referred to as a xe2x80x9c1 value,/FG method), and the case where one bit of data is assigned (1 bit/FG method). According to the 1 value/FG method, an appropriate electric potential is applied to a control gate electrode, whereby a current value in proportion to the number of formed channels is read. In the case where there are k (k is an integer of 1 or more) floating gate electrodes, (k+1) value of data can be stored in one memory transistor. On the other hand, according to the 1 bit/FG method, during read, an appropriate electric potential is applied to a control gate electrode, while an appropriate potential difference is applied between two pinning regions interposing a channel forming region to be selected and another pinning region. Consequently, a current value reflecting the state of a floating gate electrode to be selected can be read, and one bit of information can be stored per floating gate electrode.
The 1 bit/FG method uses characteristic in which in the case where a voltage is applied to pinning regions interposing a channel forming region, a threshold voltage of a selected channel forming region is shifted. This characteristic is effective when a channel width is very small, and it is desirable that a width of a channel forming region is 0.01 to 1 xcexcm (preferably, 0.01 to 0.5 xcexcm).
The structure of the present invention will be described below.
There is provided a nonvolatile memory comprising a memory transistor which includes a source region, a drain region and an active region that are formed of a single crystal semiconductor,
characterized in that the active region is composed of a plurality of impurity regions provided in a stripe shape in a channel length direction and a plurality of intrinsic or substantially intrinsic channel forming regions interposed between the plurality of impurity regions, and
the memory transistor stores triple or more-valued data.
There is provided a nonvolatile memory comprising a memory transistor which includes a source region, a drain region and an active region that are formed of a single crystal semiconductor and in which a first gate insulating film, a plurality of floating gate electrodes, a second gate insulating film, and a control gate electrode are stacked (laminated) over the active region,
characterized in that the active region is composed of a plurality of impurity regions provided in a stripe shape in a channel length direction and a plurality of intrinsic or substantially intrinsic channel forming regions interposed between the plurality of impurity regions,
the plurality of floating gate electrodes are provided over the plurality of channel forming regions in one-to-one correspondence via the first gate insulating film,
the control gate electrode is provided so as to be overlapped with the plurality of floating gate electrodes via the second gate insulating film, and
the memory transistor stores triple or more-valued data.
There is provided a nonvolatile memory comprising a memory transistor which includes a source region, a drain region and an active region formed of a single crystal semiconductor and in which a first gate insulating film, a plurality of floating gate electrodes, a second gate insulating film, and a control gate electrode are stacked over the active region,
characterized in that the active region is composed of a plurality of impurity regions provided in a stripe shape in a channel length direction and a plurality of intrinsic or substantially intrinsic channel forming regions interposed between the plurality of impurity regions,
the plurality of floating gate electrodes are provided over the plurality of channel forming regions in one-to-one correspondence via the first gate insulating film,
the control gate electrode is provided so as to be overlapped with the plurality of floating gate electrodes via the second gate insulating film,
electric potentials of the plurality of impurity regions are independently controlled, and
the memory transistor stores triple or more-valued data.
Each of the plurality of floating gate electrodes may be partially overlapped with one of the plurality of impurity regions via the first gate insulating film.
The plurality of impurity regions provided in the active region may be formed continuously even in one or both of the source region and the drain region.
It is preferable that the plurality of impurity regions are made of an element selected from Group 13 or Group 15 of the Periodic Table.
It is preferable that the plurality of impurity regions arc made of an element selected from Group 13 or Group 15 of the Periodic Table, and suppress a depletion layer spreading from the drain region to the source region.
It is preferable that a concentration of an element contained in the plurality of impurity regions is 1xc3x971017 to 5xc3x971020 atoms/cm3.
It is preferable that a channel length of the memory transistor is 0.01 to 1 xcexcm.
It is preferable that a width of the plurality of impurity regions is 0.01 to 1 xcexcm.
It is preferable that a width of the plurality of channel forming regions is 0.01 to 1 xcexcm.
A semiconductor device utilizing the nonvolatile memory as a recording medium is provided.
A microprocessor is provided as the semiconductor device.
A display, a video camera, a goggle type display, a DVD player, a head mount display, a personal computer, a mobile phone, and a car audio system are provided as the semiconductor device.